Debug methods for hybrid CPU/FPGA systems

The combining of one or more CPU’s and an FPGA fabric on the same die is growing in popularity. Such programmable system-on-chip (PSOC) systems promise performance and development time advantages over conventional technology. They include embedded CPU’s which can be characterized as either hard cores (designed into the PSOC at manufacture time) or as soft cores (designed by the end user of the FPGA using existing FPGA resources). Current debug approaches for PSOC’s are derived from ASIC and embedded software debug methods and fail to take advantage of the special feature of PSOC’s that can simplify debugging. In addition, ASIC approaches focus on the design at the gate level and provide little to help the designer identify errors in the embedded software parts of the system. Embedded software approaches focus on the use of symbolic debuggers to debug the embedded software but ignore the FPGA parts of the system. In a PSOC design, design errors may occur in many different places — the design of the CPU, the embedded software, the FPGA-based parts of the design, or the interfaces between these various parts. This paper presents a flexible tool that allows the user to dynamically adapt the CAD tool’s behavior to the level of detail needed to track down design errors in PSOC designs. It provides for the creation of and coexistence of software source debuggers and gate level debug tools, all incorporated into the same debugging environment. A prototype PSOC debugging system based on a derivative of the JHDL CAD tool is presented which illustrates the range of debug support in both simulation and hardware execution modes that can be provided for PSOC debug. Extensions to the tool to support a wider range of embedded processors and GNU compiler tools are discussed along with conclusions and future work. Effort sponsored by the Defense Advanced Research Projects Agency (DARPA) under contract number DABT63-96-C-0047. The U.S. Government is authorized to reproduce and distribute reprints for Governmental purposes notwithstanding any copyright annotation thereon.